It starts with the following background sections:
This application note describes the Prewitt edge detection reference design.
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Prewitt Edge Detection Reference Design Directory Structure StratixII_Pro_DSP_Kit-v1.0.0 Contains the files for the Stratix II EP2S180 DSP development board Docs Contains all DSP Development Kit, Stratix II Professional Edition documentation, including board design files and this user guide Examples Contains examples for the Stratix II EP2S180 DSP development board H/W Contains hardware examples for the DSP Development Kit, Stratix II Professional Edition ReferenceDesigns Contains reference designs for the Stratix II EP2S180 Kit Tool_Flow Contains the edge detection reference design files and documentation Doc Contains the Stratix II EP2S180 Kit edge detection reference design documentation QuartusII Contains the designs used for the "Review Integration of Edge Detector Using SOPC Builder" and "Set Up Hardware & Configure EP2S180 Device" sections Software Contains designs used in the "Review Software Project in Nios II IDE" and "Rebuild & Run the Software Application" sections Simulink Contains designs used in the "Review & Simulate the Prewitt Edge Detection Design" and "Perform RTL Simulation (Optional)" sections
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When you install the software from the DSP Development Kit, Stratix II Professional Edition CD-ROM, the design files are installed in the directory structure (see Figure 1).įigure 1. The processor can be reconfigured to a different set of peripherals, memories, interfaces, and performance characteristics using the SOPC Builder tool.įor more information on the Nios II embedded processor, refer to the Nios II Processor Reference Handbook. The Nios II embedded processor features a general-purpose RISC CPU architecture. SOPC Builder automatically creates the bus arbitration logic connecting the individual components together to create an overall system.įor more information on SOPC Builder, refer to the SOPC Builder User Guide. SOPC Builder is a system development tool, allowing the user to create a Nios II system module complete with a customized set of system peripherals. Using SOPC Builder & DSP Builder Tool Flow They are optimized for use in the Quartus II software for rapid prototyping.įor more information on DSP Builder, refer to the DSP Builder User Guide. The automatically generated HDL files are at the register transfer level (RTL). DSP Builder provides a seamless design flow in which you can perform algorithmic design and system integration in MATLAB and Simulink and then port the design to hardware description language (HDL) files for use in the Quartus II software. DSP Builder is a digital signal processing (DSP) development tool that interfaces The MathWorks industry-leading system-level DSP tool Simulink with the Altera Quartus II development software. The targeted device on the Stratix II EP2S180 DSP development board is the Altera EP2S180F1020C3.įor more information on the Stratix II EP2S180 DSP development board, refer to the Stratix II EP2S180 DSP Development Board Reference Manual. In addition to the Nios II processor, the edge detection design uses custom peripherals and standard peripherals found in the SOPC Builder library, the Altera library of parameterizable modules (LPM), and custom logic. The edge detection module built in DSP Builder is seamlessly integrated into the overall system using the built-in SOPC Builder interface.
The edge detection reference design is implemented using a combination of hardware and software components. The reference design illustrates an example in which designers can decide to use several design capture tools together, such as DSP Builder and SOPC Builder. The edge detection algorithm implementation maps to just nine adders and two subtractors. The edge detection reference design uses a simple Prewitt edge detection algorithm. Instead of using multiple programmable digital signal processors, a single FPGA with an embedded Nios II processor can deliver the requisite level of computing power more cost-effectively, while simplifying board complexity.
Given the increasing processing demands, the parallel processing capabilities of Altera programmable logic devices (PLDs) make them an attractive implementation option for highly repetitive tasks found in video and imaging functions. Video and image processing typically require very high computational power. Using SOPC Builder & DSP Builder Tool FlowAugust 2005, version 1.0
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